Amit Kulkarni, Ph.D.


Postdoctoral Research Associate

ETH Zurich
Universitätstrasse 6, CAB F 73
8092 Zurich, Switzerland
Ph: +41 44 632 01 79


Email: <username>[AT]inf.ethz.ch
where my username is amit.kulkarni



Hi! my name is Amit Kulkarni. I joined Systems group in May 2018 and I am working on the FPGA IP development for the research processor called Enzian.

I did my Ph.D. at Ghent University, Belgium under the supervision of Prof. Dirk Stroobandt.


Research Interests

High-Performance Computing Architectures, Reconfigurable Computing, Computer Architecture, and Hardware Software co-design.


Ph.D. Research

My Ph.D. research was about exploring and optimizing the overheads of run-time reconfiguration technology in Field Programmable Gate Array (FPGA). Dynamic Circuit Specialization (DCS) is an optimization technique used for implementing a parameterized application on an FPGA.

An application is said to be parameterized when some of its inputs, called parameters, are infrequently changing compared to the other inputs. Instead of implementing these parameter inputs as regular inputs, in the DCS approach, these inputs are implemented as constants, and the design is optimized for these constants. When the parameter values change, the design is re-optimized for the new constant values by reconfiguring the FPGA. This technique is used to specialize and reconfigure the configuration of the FPGA on the fly to better suit the problem at hand.

My research specifically focused on improving the run-time reconfiguration speed of an FPGA that includes exploring the barriers which are responsible for the deterioration of the reconfiguration speed and optimize the same which suits to the FPGA architecture for high-speed Dynamic Circuit Specialization.


Education

Ph.D., Ghent University, Belgium
Electrical Engineering
Thesis: FPGA Structures for High Speed and Low Overhead Dynamic Circuit Specialization [Link]
Degree Conferred: September 2017

M.Sc., Chalmers University of Technology, Sweden
Integrated Electronics System Design
Thesis: Evaluation of synchronization methods in multi-clock domain systems [Link]
Degree Conferred: August 2012

B.E., Visvesvaraya Technological University, India
Electronics and Communication Engineering
Project: Intelligent Lighting systems combined with train idenfication using RF-ID
Degree Conferred: July 2008


Publications

UGent biblio : Link

Google Scholar : Link

Research Gate : Link


Awards

Dr. A. Richard Newton Young Student Fellow Design Automation Conference 2013

Best Paper Award - Reconfigurable Architecture Workshop 2016 : Link

HiPEAC Collaboration Grant 2016